Three-dimensional graphics processing is utilized in a number of applications, from electronic games, and movies to computer aided design (CAD). Conventionally, three-dimensional graphics processing includes a multi-step rendering process of transitioning from a database representation of three-dimensional objects to a pseudo realistic two-dimensional projection of the object into a display space. The process generally includes setting up a polygon model (e.g., a plurality of primitives) of objects, applying linear transformation to each primitive, culling back facing primitives, clipping the primitives against a view volume, rasterizing the primitives to a pixel coordinate set, shading/lighting the individual pixels using interpolated or incremental shading techniques, and the like. Typically, graphics processors are organized in a “deep” pipeline architecture, where each stage is dedicated to performing specific functions. A benefit of a deep pipeline architecture is that it permits fast, high quality rendering of even complex scenes.
The stages of a conventional graphics processor architecture are optimized for high-speed rendering operations (e.g., interpolating parameters, such as color, texture and depth over each two dimensional projection of a primitive). The architecture of the deep pipeline is configured in order to maximize the overall rendering throughput of the graphics processor. Generally, deep pipeline architectures have sufficient data throughput (e.g., pixel fill rate) to implement fast, high quality rendering on large display space devices of even complex scenes. For example, such conventional deep pipelines are configured to compute the various parameters required to render the pixels using multiple, high precision functions. The functions are implemented such that they generate high precision results even in those circumstances where such precision is redundant or unnecessary.
The dedicated stages of deep pipeline architectured graphics processors require a relatively high transistor count. Accordingly, conventional graphic processors require a significant chip area, resulting in relatively high costs. In addition, to achieve fast, high quality rendering in deep pipeline architectures, various stages experience periods of idle processing cycles. Many of the stages consume about the same amount of power regardless of whether they are processing pixels or idle. Accordingly, conventional graphics processors consume significant power, even if the stages are performing comparatively little processing.
As a result of cost and power consumption considerations, conventional graphics processors are unsuitable for many mobile and wireless applications (e.g., wireless phones, personal digital assistants and the like). Therefore, what is desired is a graphics processor architecture having relatively low power consumption and costs.